For read operations, matched receiver (RX) architectures are conventionally used in DDR (Double Data Rate) controllers where the delay between data path (DQ) and read strobe path (DQS) are matched. As memory data rate increases, the bandwidth of the DQ path becomes a bottleneck. An unmatched sensitive RX architecture (e.g., Strong-arm latch) can mitigate some of the bottleneck, but adds to read latency. In an unmatched RX architecture, the DQ and DQS paths are not matched.